1. Field of the Invention
This invention relates to current sources, and particularly to current sources capable of providing a second current in a constant ratio to a first current.
2. Description of the Related Art
There are many circuit applications in which a second current is needed which is in a constant ratio to a first current. Circuits which provide currents that compensate for the base currents of a differential input stage typically require the generation of a second current that varies with the input stage's tail current. If the second current closely tracks the tail current, it can be used to provide compensation currents which substantially reduce the stage's input currents.
Difficulties can arise when there is a differential voltage between the first and second current sources. For example, one way in which ratioed currents can be generated is shown in FIG. 1a. First and second transistors Qa and Qb have their emitters connected to a circuit common point and their bases connected to a common bias voltage. When so arranged, Qa and Qb conduct currents I1 and I2, respectively, with:
                    I        ⁢                                  ⁢        1                    I        ⁢                                  ⁢        2              ∝          1      +              (                              V            diff                                V            A                          )              ,where Vdiff is the differential voltage between the two collectors, and VA is the Early voltage. As the current ratio varies significantly with Vdiff, this approach is unacceptable for many applications in the differential voltage is likely to vary.
The performance of the circuit of FIG. 1a can be improved by the addition of degeneration resistors Ra and Rb in the emitter circuits of Qa and Qb, as shown in FIG. 1b. When so configured:
                    I        ⁢                                  ⁢        1                    I        ⁢                                  ⁢        2              ∝          1      +              (                                            V              diff                                      V              A                                *                                    kT              q                                                      V                deg                            +                              kT                q                                                    )              ,where Vdeg is the voltage across the degeneration resistors. Here, the variation of the current ratio with Vdiff is significantly reduced, but the addition of Ra and Rb results in the circuit requiring additional headroom.
Another way to improve the performance of the circuit of FIG. 1a is to provide cascode transistors for Qa and Qb; this is shown in FIG. 1c. Here, assuming that all the transistors have equal beta (β) values:
            I      ⁢                          ⁢      1              I      ⁢                          ⁢      2        ∝      1    +                  (                              V            diff                                β            *                          V              A                                      )            .      This approach also reduces the variation of current ratio with Vdiff, but at the expense of additional headroom and an extra bias voltage generator.
A basic current mirror can also be used to generate a second current which is proportional to a first current. However, since the output impedance of each mirror transistor is proportional to its Early voltage divided by its collector current, the mirror's output impedance will be low—causing the current ratio to vary significantly with Vdiff. This can be improved by adding emitter degeneration resistors Ra and Rb as shown in FIG. 1d, but as with the circuit of FIG. 1b, the addition of Ra and Rb results in the circuit requiring additional headroom.
Another way to improve the performance of the current mirror of FIG. 1d is to add a negative resistance circuit 10 as shown in FIG. 1e; such an arrangement is described, for example, in U.S. Pat. No. 5,587,689 to Bowers. In this configuration, emitter-coupled transistors Qc and Qd are cross-coupled, with the base of Qc and the collector of Qd connected to the emitter of Qa, and the base of Qd and the collector of Qc connected to the emitter of Qb. This arrangement creates an apparent negative resistance which acts to increase the effective resistance of emitter resistors Ra and Rb, and thereby increase the mirror's output impedance such that the variation of the I2:I1 ratio with Vdiff is reduced. However, non-linearities associated with Qc and Qd render the negative resistance circuit of FIG. 1e nonlinear and poorly controlled, thereby degrading the accuracy of the I2:I1 ratio.